SPP Tool Chain
2.6 Hardware Architecture

SPML allows the description of the target hardware architecture at a coarse granularity in order to allow partitioning, and resource allocation in a distributed application. The main concepts include compute nodes, communication ports, and communication links.

The modeling elements that are used in representing a dataflow graph are described below. The description consists of a name of the modeling element, the stereotype of the modeling element which indicates the concrete syntactic realization of the element in GME (i.e. Folder, Model, Atom, Connection, Set, etc.), an explanation of the role and purpose of modeling element, and a description of the attributes of the modeling element. For additional details on understanding the concrete syntactic constructs of GME, please refer to the GME documentation.

1.    HardwareTypes

Stereotype:

Folder

Description:

HarwareTypes is the folder to be reserved exclusively for creating hardware types model. In this folder a user can build different simple hardware type, like FPGA, CPU, AD, DA, SIM, MEM, as well as composite hardware type composed of these simple hardwares and the communication links between them. A user is expected to build the system platform by using the instance models of the hardware types created in this HardwareTypes folder.

2.    Node

Stereotype:	Model
Description:	Node is an abstract base class for the concrete hardware types to capture their common characteristics.

3.    FPGA

Stereotype:	Model
Description:	FPGA represents the FPGA type of hardware.
Attribute:	Name DataType Note ID Integer   FPGAType Enumeration:       XILINX       ALTERA       VIRTEX       OTHER   ClockSignal String   GlobalSignal String

4.    CPU

Stereotype:	Model
Description:	CPU represents the CPU type of hardware.
Attribute:	Name DataType Note ID Integer   CPUType Enumeration:       HOST       TI_C40       TI_C67       RISC_PC       PPC_V2PRO

5.    AD

Stereotype:	Model
Description:	AD represents the AD type of hardware.
Attribute:	Name DataType Note ID Integer

6.    DA

Stereotype:	Model
Description:	DA represents the DA type of hardware.
Attribute:	Name DataType Note ID Integer

7.    SIM

Stereotype:	Model
Description:	SIM represents the SIM type of hardware.
Attribute:	Name DataType Note ID Integer

8.    MEM

Stereotype:	Model
Description:	MEM represents the MEM type of hardware.
Attribute:	Name DataType Note ID Integer

9.    CommPort

Icon:
Stereotype:	Atom
Description:	CommPort represents the communication ports in the hardware type.
Attribute:	Name DataType Note PortNumber Integer   Protocol Enumeration:       C40_COMM       SERIAL       MATLAB       TCP       FPGA_AD       FPGA_LED       FPGA_MEM   InputSignals String   OutputSignals String

10.    Architecture

Stereotype:	Model
Description:	Architecture is a model for creating composite hardware type model. It can contain other hardware type plus the communication between them.

11.    Link

Stereotype:	Connection
Description:	Link is the connection between CommPorts of hardware.

12.    System
          Described in 2.1. Dataflow

13.    SArchitecture

Stereotype:	Model
Description:	Inherited from the Architecture model, SArchitecture is the model used to define the hardware architecture for the system model. The OCL constraints have been included in the meta-model that will prevent a user from creating a hardware type within a SArchitecture model, it can only contain the instance models of the hardware type created in the HardwareTypes folder.

14.    Component
          Described in 2.1. Dataflow

15.    NodeRef

Stereotype:	Reference
Description:	NodeRef is reference to the computational Node. In SPML, the dataflow needs to be mapped to the hardware and this can be modeled by using reference NodeRef. Each compute node can contain one or more references to dataflow nodes. This indicates the allocation of the dataflow node to a particular compute node.

The metamodel of the above elements in defining the hardware architecture is shown as below:

Related Information

Build HardwareTypes Library

Build SArchitecture model

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