| SPP Tool Chain | |
| 6.2.1 Xilinx Platform Studio (XPS) and the Embedded Development Kit (EDK) |
In this section, it will show how to build hardware systems by using the Xilinx Platform Studio (XPS) and the Embedded Development Kit (EDK).
1. Required Installations with current Service Packs must be compatible, including the IP from Xilinx Downloads website:
Xilinx - XPS Version 7.1
2. Launch XPS
3. Open Project Provided for ML403 Board:
system.xmp (provided as basic system)
System provided is a system that has been previously tested on a ML403 Board.
1. Subtleties to note: The timing for the system is "guaranteed" to be met for
the system provided. Some constraints and timing modules were added to help
guarantee this timing. However, due to these required modules, space limitations
my be incurred when adding additional IP. So, please be aware of these
considerations when utilizing the system.xmp and what is necessary for your
system design. This is further described in detail below.
Basic System includes the following required files for the IP:
1. system.mhs : Microprocessor Hardware Specification
2. system.mss : Microprocessor Software Specification See Below:
3. system.ucf : User Constraints File (System has
added constraints to guarantee timing in this file).
Basic System includes the following IP as seen above:
1. PPC 405
2. JTAG Controller for downloading bitstream file when system successfully
builds
3. Processor System Reset Module
4. OPB Bus
5. PLB Bus
6. PLB to OPB Bridge
7. DCM modules to guarantee clock timing
8. OPB 16550 UART
9. OPB Ethernet Controller
10. OPB Interrupt Controller for 16550 and Ethernet interrupts
11. OPB External Memory Controller (SRAM on Board)
12. OPB SystemAce Controller (optional SystemAce Loading of Bitstream)
● Advanced user's topic: not covered in this document, see User's Manual
provided with ML403 Board.
13. PLB BRAM Controller and BRAM blocks
14. PLB DDR Controller (External DDR on Board)
15. Miscellaneous Glue and Control Logic
16. OPB VandyPort (Vanderbilt IP to correctly connect to SPP)
4. Generate Libraries and BSP's for Project:
These will be used for the vxWorks image necessary to operate system. This is completed in a later step.
Tools -> Generate Libraries and BSPs (from pull down menus)
Or Press on the "Generate Libraries" radio button
5. Generate Bitstream:
This is the Hardware file that will be "downloaded" to the ML403 Board: This
executes all of the required steps to synthesize, map and place and route (par)
the hardware components.
1. Tools -> Generate Bitstream (First Time)
2.
Tools -> Update Bitstream (Optional First Time, every Subsequent Build)
Or Press on the "Generate Bitstream" or "Update Bitstream" radio button
6. Download Bitstream:
This can be done two different ways:
1.
Tools -> Download (this automatically launches ISE's Impact Tool).
Or Press on the "Download" radio button
After successful downloading a Bitstream File
("download.bit") as above and as
illustrated below:
2. Launch Xilinx ISE Impact Tool Manually
Press "Cancel"
Press "Initialize Chain" Radio Button
Then the following should happen:
Press "OK"
Press "Cancel All", since you only need to select the device to download.
Then select or click once on the Third device in the chain and highlight it
Then Right Mouse Click on the Third Device, menu should pop up, then Click "Assign New Configuration File..."
Select "download.bit" from the Project Implementation Directory, then Press "Open"
Select "download.bit", on the following pop-up menu, then Press "OK"
The following warning should pop-up, Press "OK"
Now the "download.bit" is listed under the Third Device and it is ready to be programmed.
Right Mouse Click on the Third Device, Select "Program"
Press "OK"
After pressing "OK", Programming begins as seen below:
Programming Successful is illustrated below:
